Exemplary embodiments of the present invention relate to a semiconductor design technology, and more particularly, to a circuit and method for transferring an address signal in a semiconductor memory device.
Semiconductor memory devices, such as a dynamic random access memory (DRAM), often include a redundancy circuit which replaces a defective memory cell with a redundancy memory cell, thereby improving the yield of the devices.
FIG. 1 is a layout block diagram illustrating a repair operation of a conventional semiconductor memory device.
Referring to FIG. 1, the conventional semiconductor memory device includes a plurality of banks (BANK 0, BANK 1, . . . , BANK N) 10, a plurality of repair address generation unit 30, and a plurality of cell line decoding units 20. Each of the banks (BANK 0, BANK 1, . . . , BANK N) 10 includes a normal cell region and a redundancy cell region. The repair address generation units 30 are configured to generate repair address signals BANK<0:N>_REPAIR_ADD<0:15> in response to normal address signal BANK<0:N>_NORMAL_ADD<a:n>, and generate repair address use judgment signals BANK<0:N>_REPAIR_USE_JUDG whose values are determined according to whether the generated repair address signals BANK<0:N>_REPAIR_ADD<0:15> are to be used. When the repair address use judgment signals BANK<0:N>_REPAIR_USE_JUDG are deactivated, the cell line decoding units 20 selectively drive one of a plurality of local cell lines BANK<0:N>_NORMAL_CELL_LINE<0:2N>, which are provided in the normal cell regions of banks corresponding to the normal address signals BANK<0:N>_NORMAL_ADD<a:n> among the plurality of banks (BANK 0, BANK 1, . . . , BANK N) 10. When the repair address use judgment signals BANK<0:N>_REPAIR_USE_JUDG are activated, the cell line decoding units 20 selectively drive one of a plurality of local cell lines BANK<0:N>_REPAIR_CELL_LINE<0:15>, which are provided in the redundancy cell regions of banks corresponding to the normal address signals BANK<0:N>_NORMAL_ADD<a:n> among the plurality of banks (BANK 0, BANK 1, . . . , BANK N) 10, according to the repair address signals BANK<0:N>_REPAIR_ADD<0:15>.
The normal address signals BANK<0:N>_NORMAL_ADD<a:n> may be directly inputted to the plurality of cell line decoding units 20 coupled to the plurality of banks (BANK 0, BANK 1, . . . , BANK N) 10, or may pass through the plurality of repair address generation units 30 and be inputted to the cell line decoding units 20 as the repair address signals BANK<0:N>_REPAIR_ADD<0:15> and the repair address use judgment signals BANK<0:N>_REPAIR_USE_JUDG.
In addition, the repair address generation units 30 are disposed close to the banks 10 and the cell line decoding units 20, and transfer the repair address signals BANK<0:N>_REPAIR_ADD<0:15> and the repair address use judgment signals BANK<0:N>_REPAIR_USE_JUDG generated in response to the normal address signals BANK<0:N>_NORMAL_ADD<a:n>.
In this case, lines for transferring the normal address signals BANK<0:N>_NORMAL_ADD<a:n> directly inputted to the cell line decoding units 20 coupled to the banks 10 are disposed in such a manner that they do not overlap the regions where the repair address generation units 30 are disposed. Such an arrangement prevents/reduces interference with normal operation of a plurality of fuse circuits which may be provided inside the repair address generation units 30.
That is, after the semiconductor memory device is fabricated, the fuse circuit provided in the semiconductor memory device determines in a test operation whether or not to cut fuses. At this time, if lines cross over or other circuits are present over the regions overlapped with the regions where the fuse circuits are disposed, a normal test cannot be performed. Therefore, according to an example, no circuits and lines are disposed over the regions overlapped with the regions where the fuse circuits are disposed.
Such a layout of the conventional semiconductor memory device may be efficiently used when the number of lines for transferring the normal address signals BANK<0:N>_NORMAL_ADD<a:n> is not large, and the integration density of the semiconductor memory devices is relatively low.
However, as the capacity and integration density of the semiconductor memory devices increase, modifications to the above-described semiconductor memory devices are desired.
For example, FIG. 2 is a layout block diagram illustrating a repair operation of a conventional semiconductor memory device.
Referring to FIG. 2, an overall configuration is substantially identical to that corresponding to the layout of the semiconductor memory device of FIG. 1.
That is, the semiconductor memory device includes a plurality of banks (BANK 0, BANK 1, . . . , BANK N) 10, a repair address generation unit 40, and a plurality of cell line decoding units 20.
However, only one repair address generation unit 40 is separately disposed in an independent region of the semiconductor memory device, without regard to the banks 10 and the cell line decoding units 20, as opposed to the case in which the plurality of repair address generation units 30 are disposed close to the banks 10 and the cell line decoding units 20, as shown in FIG. 1.
That is, the plurality of repair address generation units 40 corresponding to the plurality of banks (BANK 0, BANK 1, . . . , BANK N) 10 are collectively located at a region to thereby provide a single repair address generation unit 40. In this way, the region where a single repair address generation unit 40 is disposed can be selected as not to overlap with the region over which the normal address signals BANK<0:N>_NORMAL_ADD<a:n> are transferred to the banks 10 and the cell line decoding units 20. Thus, the normal address signals BANK<0:N>_NORMAL_ADD<a:n> can be stably transmitted to the banks 10 and the cell line decoding units 20 while using less space.
In the layout of the conventional semiconductor memory device of FIG. 2, the region over which the single repair address generation unit 40 does not to overlap the region over which the normal address signals BANK<0:N>_NORMAL_ADD<a:n> are transferred. However, relatively long transmission lines are used in transferring the repair address signals BANK<0:N>_REPAIR_ADD<0:15> and the repair address use judgment signals BANK<0:N>_REPAIR_USE_JUDG from the repair address generation unit 30 to the banks 10 and the cell line decoding units 20. It is noted that, in FIG. 2, the length of transmission lines from the single repair address generation unit 40 disposed in a peripheral region to the banks 10 and the cell line decoding units 20 disposed in a core region is not proportionally depicted due to the limited space for the drawings. The actual length of transmission lines from the peripheral region to the core region is significantly longer than the length of transmission lines used to transfer the normal address signals BANK<0:N>_NORMAL_ADD<a:n> within the core region.
If there was only one bank 10, the length of transmission lines for transferring the repair address signals BANK<0:N>_REPAIR_ADD<0:15> and the repair address use judgment signals BANK<0:N>_REPAIR_USE_JUDG from the repair address generation unit 30 to the banks 10 and the cell line decoding units 20 do not raise a significant concern.
However, as illustrated in FIGS. 1 and 2, the plurality of banks (BANK 0, BANK 1, . . . , BANK N) 10 may be present in the semiconductor memory device, and therefore, the transmission lines for transmitting the repair address signals BANK#_REPAIR_ADD<0:15> and the repair address use judgment signals BANK#_REPAIR_USE_JUDG are to be provided in each bank. Consequently, the size of the semiconductor memory device is increased. For the purpose of this disclosure, “#” is one value ranging from 0 to N.
More specifically, in the conventional semiconductor memory device of FIG. 2, the transmission lines for receiving the repair address signals BANK<0:N>_REPAIR_ADD<0:15> and the repair address use judgment signals BANK<0:N>_REPAIR_USE_JUDG raise more concerns than the transmission lines for receiving the normal address signals BANK<0:N>_NORMAL_ADD<a:n> for the following reasons.
First, since the normal address signals NORMAL_ADD<a:n> also contain information for selecting one of the plurality of banks (BANK 0, BANK 1, . . . , BANK N) 10, the plurality of banks (BANK 0, BANK 1, . . . , BANK N) 10 can share the transmission lines for receiving the normal address signals BANK#_NORMAL_ADD<a:n> after performing the operation of pre-decoding the normal address signals NORMAL_ADD<a:n>. Therefore, “n−a+1” transmission lines are required for transferring the normal address signals BANK<0:N>_NORMAL_ADD<a:n> to the plurality of banks (BANK 0, BANK 1, . . . , BANK N) 10.
On the other hand, the repair address signals BANK<0:N>_REPAIR_ADD<0:15> and the repair address use judgment signals BANK<0:N>_REPAIR_USE_JUDG are specific to each of the plurality of banks (BANK 0, BANK 1, . . . , BANK N) 10, and they are transferred to the respective banks through respective transmission lines. Therefore, “(15+1)×N” transmission lines are required in order to transfer the repair address signals BANK<0:N>_REPAIR_ADD<0:15> and the repair address use judgment signals BANK<0:N>_REPAIR_USE_JUDG to the plurality of banks (BANK 0, BANK 1, . . . , BANK N) 10. The value of “N” may increase as the number of the banks increases.
Therefore, in the case of devices having a large number of banks, the integration density of the devices are reaching limits.